The present invention relates generally to string digital-to-analog converters (string DACs) and associated interpolation circuits thereof, and more particularly to circuitry and techniques for calibrating interpolating string DACs to correct integral nonlinearity (INL) errors.
The assignee""s U.S. Pat. No. 6,246,351 issued Jun. 12, 2001 entitled xe2x80x9cLSB Interpolation Circuits and Method for Segmented Digital-to-Analog Converterxe2x80x9d, incorporated herein by reference, and U.S. Pat. No. 6,496,133 issued Dec. 17, 2002 entitled xe2x80x9cResistor String Integrated Circuit and Method for Reduced Linearity Errorxe2x80x9d, both by the present inventor, are generally indicative of the state of the art for interpolating string DACs.
Monotonicity and low INL are usually required in applications in which DACs, including string DACs, are used. The INL error is the difference between the actual output of a DAC and the xe2x80x9cidealxe2x80x9d output of the DAC. Resistor mismatches in string DACs cause INL error. String DACs are commonly fabricated using submicron CMOS technologies wherein it is expensive to utilize precision resistors to ensure monotonicity of the DAC, because manufacture of the precision resistors requires expensive laser trimming operations. The matching of the resistors used in the xe2x80x9cstringxe2x80x9d section of a string DAC limits the INL of a string DAC. With careful layout of the string resistors, 10-bit accuracy of the matching of the resistances of the string resistors is possible in the present state-of-to-art CMOS fabrication processes. Therefore, the INL of a 16-bit interpolating string DAC will be at the 64 LSB level. This means the output of the DAC may be as much as 64 LSBs different than what an ideal DAC would produce, which is unacceptably large for some applications.
Next, the structure and operation of a basic conventional interpolating string DAC will be described. Referring to prior art FIG. 1, a 4-bit interpolating string DAC 1 includes a 2-bit coarse string DAC 2, the output of which is interpolated by 2-bit interpolator DAC 6. The coarse string DAC 2 includes a resistor string 25 including four equal-resistance series-connected resistors R1, R2, R3, and R4 and tap points 4-1,2,3, and 4 therebetween. The voltages on nodes 4-1,2,3,4 of the resistor string are assumed to be 48, 56, 108, and 128 xe2x80x9cvoltage unitsxe2x80x9d. Each of the voltage units referred to is equal to the reference voltage divided by the number of string resistors. Typically, the reference voltage is 1.5 volts, 2.5 volts, or 5 volts. Coarse string DAC 2 produces two output levels Vhigh and Vlow which are the voltage of the upper terminal and lower terminal, respectively, of a selected one of the series-connected resistors R1-R4 that constitute the resistor string of coarse string DAC 2. The resistor referred to is selected in response to the MSB code b3b2 of the digital input provided to string DAC 1.
The output of coarse string DAC 2 is applied to the input of an interpolation DAC 6, which interpolates to produce a voltage level that is proportionately between Vhigh and Vlow in response to the LSBs b1b0 of the digital input word applied to string DAC 1. The structure and operation of string DAC 1 are set forth in detail in above-mentioned U.S. Pat. No. 6,246,351 issued Jun. 12, 2001 entitled xe2x80x9cLSB Interpolation Circuits and Method for Segmented Digital-to-Analog Converterxe2x80x9d, which is incorporated herein by reference.
The example of prior art FIG. 1 shows a 2-bit interpolator, but the basic approach can be applied to an n-bit interpolator. Level selection switches 5 operate to connect the input of the interpolator 6 to two consecutive voltages, Vhigh and Vlow. The number of gm stages 8-1,2,3,4 having an input connected to Vhigh is equal to the decimal value of the LSB digital input b1b0 that is applied to interpolating switch matrix 7. In other words, the interpolating switch matrix 7 functions as a thermometer decoder. If b1 and b0 both are equal to zero, all of the (+) inputs of interpolator DAC 6 are connected to Vlow, and the output Vout will then be equal to Vlow. If the digital input to the switching matrix 7 is 01, then the (+) input of one of the gm stages 8-1,2, 3,4 is connected to Vhigh. Since one of 4 of the (+) inputs is connected to Vhigh, that gm stage adds an offset as indicated in the following equation:
Vout=Vlow+(Vhighxe2x88x92Vlow)/4(b1b0=01)
When the LSB digital input b1b0 is 10, two of the four (+) inputs of the gm inputs are connected to Vhigh. This causes interpolation DAC 6 to add yet another offset voltage to the output as indicated in the following equation:
Vout=Vlow+2*(Vhighxe2x88x92Vlow)/4(b1b0=10)
When the LSB digital input b1b0 is 11, three of the four (+) inputs of the gm stage are connected to Vhigh. This causes interpolation DAC 6 to add yet another offset voltage to the output as indicated in the following equation:
Vout=Vlow+3*(Vhighxe2x88x92Vlow)/4(b1b0=11)
In general, for an N-bit interpolator, when k of the positive inputs (or thermometer-decoded LSBs) are connected to Vhigh, Vout will be given by the following equation:
Vout =Vlow+k*(Vhighxe2x88x92Vlow)/2N.
The foregoing equation indicates that linear interpolation is achieved between Vhigh and Vlow.
Thus, there is an unmet need for a circuit and method for reducing the INL of an interpolating string DAC, especially for an interpolating string DAC having a resolution of 16 bits or greater.
There also is an unmet need for a circuit and method for reducing the INL of an interpolating string DAC having a resolution of 16 bits or greater without use of precision resistors or laser trimming of resistors.
There also is an unmet need for an inexpensive interpolating string DAC, especially one having a resolution of 16 bits or greater, having very low integral nonlinearity.
There also is an unmet need for an inexpensive interpolating string DAC, especially one that has a resolution of 16 bits or greater and is compatible with present CMOS technologies.
Therefore, it is an object of the present invention to provide an inexpensive interpolating string DAC having very low integral nonlinearity, especially one having a resolution of 16 bits or greater.
It is another object of the present invention to provide a circuit and method for reducing the INL of an interpolating string DAC, especially for an interpolating string DAC having a resolution of 16 bits or greater.
It is another object of the present invention to provide a circuit and method for reducing the INL of an interpolating string DAC having a resolution of 16 bits or greater without use of precision resistors or laser trimming of resistors.
It is another object of the invention to provide an inexpensive interpolating string DAC that is suitable for manufacturing using a low-cost CMOS process.
Briefly described, and in accordance with one embodiment, the present invention provides an M+N bit DAC includes an N-bit interpolation circuit for interpolating between a first voltage (Vhigh) on a first conductor (17A) and a second voltage (Vlow) on a second conductor (17B), an output amplifier (10), a calibration interpolation circuit (14), a memory circuit (36) for storing error information corresponding to various values of the first voltage and second voltage, outputs of the N-bit interpolation circuit and the calibration interpolation circuit being coupled to inputs of the output amplifier, and switching circuitry responsive to a N-bit portion of a M+N input word coupling the memory to inputs of the of the calibration interpolation circuit so as to correct integral nonlinearity errors associated with the various values of the first and second voltages.
In the described embodiment, the invention provides an interpolation circuit for interpolating between a first voltage (Vhigh) on a first conductor (17A) and a second voltage (Vlow) on a second conductor (17B), including a plurality of differential voltage-to-current converter circuits (8-1,2,3,4) each including a first transistor and a second transistor each having a source coupled to a corresponding current source, an output amplifier (10) having first and second inputs coupled to drains of various first and second transistors, respectively, the output amplifier producing an output voltage coupled to a gate of each of the second transistors, a first switch circuit (7) adapted to selectively couple gates of various first transistors to one configured of the first conductor (17A) and the second conductor (17B) in response to a plurality of digital bit signals (b1b0), respectively, and a calibration interpolation circuit (14) including a plurality of differential voltage-to-current converter circuits (13-1,2,3,4) each including a first transistor and a second transistor each having a source coupled to a corresponding current source, a memory circuit (36) coupled to a third conductor (Vhclb) and a fourth conductor (Vlclb) for storing error information corresponding to various values of the first voltage (Vhigh) and second voltage (Vlow) and accessible to provide stored error correction information on the third (Vhclb) and fourth (Vlclb) conductors, a second switch circuit (21) adapted to selectively couple gates of various first transistors of the plurality of differential voltage-to-current converter circuits (13-1,2,3,4) of the calibration interpolation circuit to one configured of the third conductor (Vhclb) and the fourth conductor (Vlclb) in response to the plurality of digital bit signals (b1b0), respectively, and a drain of each of the first transistors of the calibration interpolation circuit (14) being coupled to the first input of the output amplifier and a drain of each of the second transistors of the calibration interpolation circuit being coupled to the second input of the output amplifier so as to cause the output amplifier to produce a value of the output voltage that is corrected for the errors in the various values of the first (Vhigh) and second (Vlow) voltages.
In the described embodiment, the invention provides an M+N bit digital-to-analog converter (DAC) for converting an M+N bit input word including an M-bit MSB subword and an N-bit LSB subword to an analog output signal, including a string DAC section (2), and interpolation DAC section (6), and a calibration interpolation circuit (14). The string DAC section (2) includes a plurality of series-connected string resistors (R1-4), and an MSB subword decoding and switching circuit (5) adapted to selectively couple voltages on first and second terminals of a selected string resistor to first (17A) and second (17B) conductors in response to the MSB subword, respectively, first and second terminals of the various string resistors being coupled to various tap points of the plurality of series-connected string resistors. The interpolation DAC section (6) includes a plurality of differential converter circuits or gm circuits (8-1,2,3,4) each including a current source and a first transistor and a second transistor each having a source coupled to the current source, a first LSB subword decoding and switching circuit (7) adapted to selectively couple gates of various first transistors of the interpolation DAC section (6) to one configured of the first (17A) and second (17B) conductors in response to the LSB subword, respectively, and an output amplifier (10) having first (xe2x88x92) and second (+) inputs coupled to drains of various first transistors and second transistors of the interpolation DAC section (6) and to a load circuit (9A,B) and producing an output voltage coupled to a gate of each of the second transistors. The calibration interpolation circuit (14) includes a plurality of differential voltage-to-current converter circuits or gm circuits (13-1,2,3,4) each including a current source and a first transistor and a second transistor each having a source coupled to the current source, a memory (36) coupled to third (38A) and fourth (38B) conductors for storing tap point error information for the various tap points and accessible in response to the MSB subword to provide stored tap point error information on the third (38A) and fourth (38B) conductors, and a second LSB subword decoding and switching circuit (21) adapted to selectively couple gates of various first transistors of the plurality of differential converter circuits (13-1,2,3,4) of the calibration interpolation circuit to one of the third conductor (38A) and the fourth conductor (38B) in response to the MSB subword.
In the described embodiment, a drain of each of the first transistors of the calibration interpolation circuit (14) is coupled to the first input (xe2x88x92) of the output amplifier and a drain of each of the second transistors of the calibration interpolation circuit being coupled to the second input (+) of the output amplifier so as to cause the output amplifier to produce a value of the output voltage that is corrected for the integral nonlinearity of the M+N bit digital-to-analog converter. A voltage calibration generator circuit performs the function of generating error voltages corresponding to the various tap points and measuring error information for each tap point equal to the difference between an actual tap point voltage and an ideal tap point voltage for that tap point and storing the measured error information in the memory circuit. The memory is accessed at memory addresses determined in response to the M-bit MSB subword both to initially write the tap point error information into the memory and later to provide stored tap point error information to the third (38A) and fourth (38B) and conductors during normal operation of the M+N bit digital-to-analog converter.